There are many applications in the telecommunications field where a local clock must be synchronized to some external reference clock. This operation is typically performed with a phase locked loop.
A traditional PLL is shown in FIG. 1. In this example, the output frequency is generated by voltage controlled oscillator (VCO) 10 and fed back through a divider-by-N 16 to one input of phase detector 18, which has a second input receiving a reference clock from digital controlled oscillator (DCO) 20. The phase detector 18 obtains the phase difference between the VCO output, after division by N, where N is an integer, and the output of the DC) 20. The output of the phase detector 18, after passing through an analog low pass filter 12, is used to control the VCO 10.
The output of the phase detector 18 is a pulse with level of either −1, 0 or 1. The width of the pulse equals the time between two rising edges of the DCO output and VCO output (after division). The divisor N represents the frequency ratio between the DCO 20 and VCO 10. If the rising edge of the DCO earlier than the VCO pulse, the output of the phase detector 18 has a positive pulse. If it arrives later, the output is a negative pulse. If two rising edges arrive at the same time, the output is zero.
The DCO 20 is locked to a primary reference source as shown in FIG. 2 and forms part of a digital PLL including a divider-by-M 22, a subtractor 26 for deriving the phase difference between the feedback signal and the reference source, and a digital low pass filter 24. The output of the DC) 20 is a pulse which is produced whenever the DCO counter value reaches a predetermined threshold. The DCO outputs complete phase information or the whole DCO value. As in FIG. 1, the divider M represents the frequency ratio between DCO and reference signal.
Subtractor 26 compares the DCO phase with the input reference phase, and the resulting phase error is filtered by digital low pass filter 24 and used to adjust the frequency of the DCO 20.
The DCO frequencies fDCO (FIG. 1) and fDCO1 (FIG. 2) can be the same value or can be a scaled difference.
Since the DCO 20 is locked to the primary reference source and the VCO 10 is locked to the DCO 20, it follows that the VCO is also locked to the primary reference source. The quality of the frequency lock is measured is measured by jitter (short term variations) and wander (long term variations). The digital filter shown in FIG. 2 is a very important element in the reduction of phase error. For a small amount of jitter, say less than 1 ps, the filter should have a very small bandwidth, typically less than 1 Hz. However, the use of such a low bandwidth filter means that it will take a very long time to acquire frequency lock.
Prior art implementations are also complex and not well suited for circuit integration.